Demande d'aide pour instaler l'environement d'un FPGA

Demande d'aide pour instaler l'environement d'un FPGA - Divers - Programmation

Marsh Posté le 08-04-2016 à 11:13:56    

Bonjours,
 
Pour mon stage de fin d'étude je dois reprogrammer un FPGA (Kintex 7 XC7K410T) du USRP X310 pour créé un compteur permettant de commander l’acquisition des capteurs pour augmenter la vitesse de l'acquisition générale.
Pour le moment j'ai réalisé ces manip' : (c'est ma fiche compte rendu)
 

Citation :

Il faut suivre les instructions de la doc :  
 
1- Télécharger et installer le logiciel Xilinx Vivado 2015.4 Il faut bien récupérer la suite Vivado
« Design Suite - HLx Editions - Single File Download ».  
J’ai suivi les instructions, il est donc installé dans /opt/Xilinx. L’aide d’installation est utile, je l’ai utilisé pour bien installer ce qu’il faut.
 
2- Télécharger et installer GNU Make, prendre la dernière version car la 3.6 est trop vielle.
 
3- Télécharger GNU Bash, j’ai pris la version 4.0 mais je pense que la dernière version peut être
utilisé.
 
4- J’ai installé Doxygen car c’est assez simple, il suffit d’entrer la commande : «  sudo apt-get
install python bash build-essential doxygen »
 
5- Pour la construction d’instruction il faut tout d’abord télécharger le fichier source. Puis aller via la console dans usrp3/top/x300 et utiliser la commande « source setupenv.sh ». Entrer ensuite la commande « make ». Normalement les instructions se construisent. Moi ça ne fonctionne pas pour le moment


 
Mon problème c'est quand je lance le "make" il me commence la construction mais il me met plein de message WARNING ou CRITICAL WARNING.
 
Est ce que vous avez une idée de ce que je ne fait pas bien.
 
Voici les imprim' écran de la console
 
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et en code :  

Code :
  1. rlecornec@open-cs-dell-r220:/opt/fpga-master/usrp3/top/x300$ make
  2. make -f Makefile.x300.inc bin NAME=X300_HGS ARCH=kintex7 PART_ID=xc7k325t/ffg900/-2 ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16  VERILOG_DEFS="ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16 "
  3. make[1]: entrant dans le répertoire « /opt/fpga-master/usrp3/top/x300 »
  4. BUILDER: Checking tools...
  5. * GNU bash, version 4.0.0(1)-release (x86_64-unknown-linux-gnu)
  6. * Python 2.7.6
  7. * Vivado v2015.4 (64-bit)
  8. ========================================================
  9. BUILDER: Building IP ten_gig_eth_pcs_pma
  10. ========================================================
  11. BUILDER: Staging IP in build directory...
  12. BUILDER: Reserving IP location: /opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma
  13. BUILDER: Retargeting IP to part kintex7/xc7k325t/ffg900/-2...
  14. BUILDER: Building IP...
  16. ****** Vivado v2015.4 (64-bit)
  17.   **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
  18.   **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
  19.     ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
  21. source /opt/fpga-master/usrp3/tools/scripts/viv_generate_ip.tcl
  22. # set xci_file         $::env(XCI_FILE)               ;
  23. # set part_name        $::env(PART_NAME)              ;
  24. # set gen_example_proj $::env(GEN_EXAMPLE)            ;
  25. # set synth_ip         $::env(SYNTH_IP)               ;
  26. # set ip_name [file rootname [file tail $xci_file]]   ;
  27. # file delete -force "$xci_file.out"
  28. # create_project -part $part_name -in_memory -ip
  29. # set_property target_simulator XSim [current_project]
  30. # add_files -norecurse -force $xci_file
  31. INFO: [IP_Flow 19-234] Refreshing IP repositories
  32. INFO: [IP_Flow 19-1704] No user IP repositories specified
  33. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.4/data/ip'.
  34. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.dcp'. Please regenerate to continue.
  35. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.v'. Please regenerate to continue.
  36. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.vhdl'. Please regenerate to continue.
  37. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.vhdl'. Please regenerate to continue.
  38. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.v'. Please regenerate to continue.
  39. # reset_target all [get_files $xci_file]
  40. # puts "BUILDER: Generating IP Target..."
  41. BUILDER: Generating IP Target...
  42. # generate_target all [get_files $xci_file]
  43. INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'ten_gig_eth_pcs_pma'...
  44. INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'ten_gig_eth_pcs_pma'...
  45. WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
  46. WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
  47. INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'ten_gig_eth_pcs_pma'...
  48. WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
  49. WARNING: [IP_Flow 19-650] IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a Design_Linking license.
  50. INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'ten_gig_eth_pcs_pma'...
  51. # if [string match $synth_ip "1"] {
  52. #     puts "BUILDER: Synthesizing IP Target..."
  53. #     synth_ip [get_ips $ip_name]
  54. # }
  55. BUILDER: Synthesizing IP Target...
  56. INFO: [IP_Flow 19-234] Refreshing IP repositories
  57. INFO: [IP_Flow 19-1704] No user IP repositories specified
  58. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.4/data/ip'.
  59. Command: synth_design -top ten_gig_eth_pcs_pma -part xc7k325tffg900-2 -mode out_of_context
  60. Starting synth_design
  61. Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
  62. WARNING: [Common 17-348] Failed to get the license for feature 'Synthesis' and/or device 'xc7k325t'
  63. 1 Infos, 1 Warnings, 0 Critical Warnings and 1 Errors encountered.
  64. synth_design failed
  65. ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7k325t'. Please run the Vivado License Manager for assistance in determining
  66. which features and devices are licensed for your system.
  67. Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ".
  68. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
  69. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
  70. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
  71. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
  72. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
  73. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
  74. ERROR: [Vivado 12-398] No designs are open
  75. ****** Webtalk v2015.4 (64-bit)
  76.   **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
  77.   **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
  78.     ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
  80. source /opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/.Xil/Vivado-19361-open-cs-dell-r220/webtalk/labtool_webtalk.tcl -notrace
  81. INFO: [Common 17-206] Exiting Webtalk at Fri Apr  8 12:11:30 2016...
  82. INFO: [Vivado 12-3441] generate_netlist_ip - operation complete
  83. # if [string match $gen_example_proj "1"] {
  84. #     puts "BUILDER: Generating Example Design..."
  85. #     open_example_project -force -dir . [get_ips $ip_name]
  86. # }
  87. BUILDER: Generating Example Design...
  88. INFO: [IP_Flow 19-1686] Generating 'Examples' target for IP 'ten_gig_eth_pcs_pma'...
  90. ****** Vivado v2015.4 (64-bit)
  91.   **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
  92.   **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
  93.     ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
  95. source /opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_ex.tcl
  96. # set srcIpDir "/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma"
  97. # create_project -name ten_gig_eth_pcs_pma_example -force
  98. # set_property part xc7k325tffg900-2 [current_project]
  99. # set_property target_language verilog [current_project]
  100. # set_property simulator_language MIXED [current_project]
  101. # set_property coreContainer.enable false [current_project]
  102. # set returnCode 0
  103. # import_ip -files [list [file join $srcIpDir ten_gig_eth_pcs_pma.xci]] -name ten_gig_eth_pcs_pma
  104. INFO: [IP_Flow 19-234] Refreshing IP repositories
  105. INFO: [IP_Flow 19-1704] No user IP repositories specified
  106. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.4/data/ip'.
  107. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.dcp'. Please regenerate to continue.
  108. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.v'. Please regenerate to continue.
  109. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.vhdl'. Please regenerate to continue.
  110. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.vhdl'. Please regenerate to continue.
  111. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.v'. Please regenerate to continue.
  112. CRITICAL WARNING: [IP_Flow 19-4299] Failed to copy '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.dcp' to '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.srcs/sources_1/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.dcp'
  113. CRITICAL WARNING: [IP_Flow 19-4299] Failed to copy '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.v' to '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.srcs/sources_1/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.v'
  114. CRITICAL WARNING: [IP_Flow 19-4299] Failed to copy '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.vhdl' to '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.srcs/sources_1/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.vhdl'
  115. CRITICAL WARNING: [IP_Flow 19-4299] Failed to copy '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.vhdl' to '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.srcs/sources_1/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.vhdl'
  116. CRITICAL WARNING: [IP_Flow 19-4299] Failed to copy '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.v' to '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.srcs/sources_1/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_sim_netlist.v'
  117. # reset_target {open_example} [get_ips ten_gig_eth_pcs_pma]
  118. # proc _filter_supported_targets {targets ip} {
  119. #   set res {}
  120. #   set all [get_property SUPPORTED_TARGETS $ip]
  121. #   foreach target $targets {
  122. #     lappend res {*}[lsearch -all -inline -nocase $all $target]
  123. #   }
  124. #   return $res
  125. # }
  126. # generate_target -quiet [_filter_supported_targets {instantiation_template synthesis simulation implementation shared_logic} [get_ips ten_gig_eth_pcs_pma]] [get_ips ten_gig_eth_pcs_pma]
  127. # add_files -scan_for_includes -quiet -fileset [current_fileset] \
  128. #   [list [file join $srcIpDir example_design/ten_gig_eth_pcs_pma_example_design.v]] \
  129. #   [list [file join $srcIpDir example_design/support/ten_gig_eth_pcs_pma_support.v]] \
  130. #   [list [file join $srcIpDir example_design/support/ten_gig_eth_pcs_pma_ff_synchronizer_rst2.v]] \
  131. #   [list [file join $srcIpDir example_design/support/ten_gig_eth_pcs_pma_shared_clock_and_reset.v]] \
  132. #   [list [file join $srcIpDir example_design/support/ten_gig_eth_pcs_pma_gt_common.v]]
  133. # add_files -quiet -fileset [current_fileset -constrset] \
  134. #   [list [file join $srcIpDir example_design/ten_gig_eth_pcs_pma_example_design.xdc]]
  135. # if { [catch {current_fileset -simset} exc] } { create_fileset -simset sim_1 }
  136. # add_files -quiet -scan_for_includes -fileset [current_fileset -simset] \
  137. #   [list [file join $srcIpDir simulation/demo_tb.v]]
  138. # set_property USED_IN_SYNTHESIS false [get_files [list [file join $srcIpDir simulation/demo_tb.v]]]
  139. # import_files
  140. INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'constrs_1'
  141. INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sim_1'
  142. INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'
  143. # set_property TOP [lindex [find_top] 0] [current_fileset]
  144. # update_compile_order -fileset [current_fileset]
  145. # update_compile_order -fileset [current_fileset -simset]
  146. # generate_target -quiet all [concat [ get_ips -quiet -filter scope=={} ] [get_files -quiet *bd ] ]
  147. # export_ip_user_files -force
  148. INFO: [exportsim-Tcl-35] Exporting simulation files for "XSIM" (Xilinx Vivado Simulator)...
  149. INFO: [exportsim-Tcl-29] Script generated: '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/xsim/ten_gig_eth_pcs_pma.sh'
  150. INFO: [exportsim-Tcl-25] Exported '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/xsim/configure_gt.tcl'
  151. INFO: [exportsim-Tcl-35] Exporting simulation files for "MODELSIM" (Mentor Graphics ModelSim Simulator)...
  152. INFO: [exportsim-Tcl-29] Script generated: '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/modelsim/ten_gig_eth_pcs_pma.sh'
  153. INFO: [exportsim-Tcl-25] Exported '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/modelsim/configure_gt.tcl'
  154. INFO: [exportsim-Tcl-35] Exporting simulation files for "QUESTA" (Mentor Graphics Questa Advanced Simulator)...
  155. INFO: [exportsim-Tcl-29] Script generated: '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/questa/ten_gig_eth_pcs_pma.sh'
  156. INFO: [exportsim-Tcl-25] Exported '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/questa/configure_gt.tcl'
  157. INFO: [exportsim-Tcl-35] Exporting simulation files for "IES" (Cadence Incisive Enterprise Simulator)...
  158. INFO: [exportsim-Tcl-29] Script generated: '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/ies/ten_gig_eth_pcs_pma.sh'
  159. INFO: [exportsim-Tcl-25] Exported '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/ies/configure_gt.tcl'
  160. INFO: [exportsim-Tcl-35] Exporting simulation files for "VCS" (Synopsys Verilog Compiler Simulator)...
  161. INFO: [exportsim-Tcl-29] Script generated: '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/vcs/ten_gig_eth_pcs_pma.sh'
  162. INFO: [exportsim-Tcl-25] Exported '/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma_example/ten_gig_eth_pcs_pma_example.ip_user_files/sim_scripts/ten_gig_eth_pcs_pma/vcs/configure_gt.tcl'
  163. # set dfile "/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/oepdone.txt"
  164. # set doneFile [open $dfile w]
  165. # puts $doneFile "Open Example Project DONE"
  166. # close $doneFile
  167. # if { $returnCode != 0 } {
  168. #   error "Problems were encountered while executing the example design script, please review the log files."
  169. # }
  170. INFO: [Common 17-206] Exiting Vivado at Fri Apr  8 12:11:37 2016...
  171. open_example_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1032.035 ; gain = 0.000 ; free physical = 5252 ; free virtual = 14753
  172. # close_project
  173. # if { [get_msg_config -count -severity ERROR] == 0 } {
  174. #     # Write output cookie file
  175. #     set outfile [open "$xci_file.out" w]
  176. #     puts $outfile "This file was auto-generated by viv_generate_ip.tcl and signifies that IP generation is done."
  177. #     close $outfile
  178. # } else {
  179. #     exit 1
  180. # }
  181. INFO: [Common 17-206] Exiting Vivado at Fri Apr  8 12:11:38 2016...
  182. BUILDER: Releasing IP location: /opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma
  183. make[1]: *** [/opt/fpga-master/usrp3/top/x300/build-ip/xc7k325tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] Erreur 1
  184. make[1]: quittant le répertoire « /opt/fpga-master/usrp3/top/x300 »
  185. make: *** [X300_HGS] Erreur 2


 
Voilà si vous avez des idées ou des conseils je suis vraiment preneur.
 
Merci


Message édité par rochazer le 08-04-2016 à 12:18:37
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Marsh Posté le 08-04-2016 à 11:13:56   

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Marsh Posté le 08-04-2016 à 18:37:43    

Problème de permission ?


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On croit souvent avoir vu le fond de la stupidité humaine, et il parfois nécessaire qu'on vous rappelle qu'elle n'a pas de fond.
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